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HM514800C Series HM51S4800C Series
524,288-word x 8-bit Dynamic Random Access Memory
Description
The Hitachi HM51(S)4800C are CMOS dynamic RAM organized as 524,288-word x 8-bit. HM51(S)4800C have realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4800C offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM51(S)4800C to be packaged in standard 400-mil 28-pin plastic SOJ and standard 400-mil 28-pin plastic TSOPII. Internal refresh timer enables HM51S4800C self refresh operation.
Features
* Single 5 V ( 10%) * High speed Access time: 60 ns/70 ns/80 ns (max) * Low power dissipation Active mode: 605 mW/550 mW/495 mW (max) Standby mode: 11 mW (max) 1.1 mW (max) (L-version) * Fast page mode capability * 1,024 refresh cycles: 16 ms 128 ms (L-version) * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * Battery backup operation (L-version) * Self refresh operation (HM51S4800C)
HM514800C, HM51S4800C Series
Ordering Information
Type No. HM514800CJ-6 HM514800CJ-7 HM514800CJ-8 HM514800CLJ-6 HM514800CLJ-7 HM514800CLJ-8 HM51S4800CJ-6 HM51S4800CJ-7 HM51S4800CJ-8 HM51S4800CLJ-6 HM51S4800CLJ-7 HM51S4800CLJ-8 HM514800CTT-6 HM514800CTT-7 HM514800CTT-8 HM514800CLTT-6 HM514800CLTT-7 HM514800CLTT-8 HM51S4800CTT-6 HM51S4800CTT-7 HM51S4800CTT-8 HM51S4800CLTT-6 HM51S4800CLTT-7 HM51S4800CLTT-8 Access Time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 400-mil 28-pin plastic TSOP II (TTP-28D) Package 400-mil 28-pin plastic SOJ (CP-28D)
2
HM514800C, HM51S4800C Series
Pin Arrangement
HM514800CJ/CLJ Series HM51S4800CJ/CLJ Series VCC I/O0 I/O1 I/O2 I/O3 NC WE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE NC A8 A7 A6 A5 A4 VSS HM514800CTT/CLTT Series HM51S4800CTT/CLTT Series VCC I/O0 I/O1 I/O2 I/O3 NC WE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (Top view) VSS I/O7 I/O6 I/O5 I/O4 CAS OE NC A8 A7 A6 A5 A4 VSS
Pin Description
Pin Name A0 - A9 Function Address input - Row address - Column address - Refresh address Data-in/data-out Row address strobe Column address strobe Read/write enable Output enable Power (+5 V) Ground
A0 - A9 A0 - A8 A0 - A9
I/O0 - I/O7 RAS CAS WE OE VCC VSS
3
4
Row Driver
Block Diagram
RAS
Row Driver
RAS Control Circuit
256 k Memory Array Mat
256 k Memory Array Mat
I/O1
I/O Bus & Column Decoder
Row Driver Row Driver
I/O Bus & Column Decoder 256 k Memory Array Mat
256 k Memory Array Mat
I/O2
CAS
Row Driver
CAS Control Circuit
Row Driver
256 k Memory Array Mat
256 k Memory Array Mat
HM514800C, HM51S4800C Series
I/O1 Buff. I/O2 Buff. I/O3 Buff. I/O4 Buff.
Row Address Buffer I/O3
I/O Bus & Column Decoder
Row Driver Row Driver
I/O Bus & Column Decoder 256 k Memory Array Mat
256 k Memory Array Mat
WE
WE Control Circuit
I/O4
Row Decoder & Peripheral Circuit
Address A0-A9
Row Driver Row Driver
256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder
Row Driver
OE
OE Control Circuit
I/O Bus & Column Decoder
Row Driver
I/O5
256 k Memory Array Mat
Row Driver
256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder
I/O6
256 k Memory Array Mat
Row Driver
Column Address Buffer
Row Driver Row Driver
I/O Bus & Column Decoder
I/O7
256 k Memory Array Mat
256 k Memory Array Mat
I/O8
I/O5 Buff. I/O6 Buff. I/O7 Buff. I/O8 Buff.
HM514800C, HM51S4800C Series
Operation Mode
The HM51(S)4800C series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle (HM51S4800C) 8. Fast page mode read cycle 9. Fast page mode early write cycle 10. Fast page mode delayed write cycle 11. Fast page mode read-modify-write cycle
Inputs RAS H H L L L L L H to L CAS H L L L L L H L WE D H H L L
*2 *2
OE D L L D H L to H D D
Output Open Valid Valid Open Undefined Valid Open Open
Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Self refresh cycle (HM51S4800C)
H to L D D
L L L L L
H to L H to L H to L H to L L
H L L
*2 *2
L D H L to H H
Valid Open Undefined Valid Open
Fast page mode read cycle Fast page mode early write cycle Fast page mode delayed write cycle Fast page mode read-modify-write cycle Read cycle (Output disabled)
H to L H
Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle
5
HM514800C, HM51S4800C Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C) *2
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage (I/O pin) (Others) VIH VIL VIL Min 0 4.5 2.4 -1.0 -2.0 Typ 0 5.0 -- -- -- Max 0 5.5 6.5 0.8 0.8 Unit V V V V V Notes 2 1, 2 1 1 1
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) *5
HM514800C, HM51S4800C -6 Parameter Operating current Standby current
*1, 2
-7 Max Min 120 2 -- --
-8 Max Min 110 2 -- -- Max Unit Test Conditions 100 2 mA mA RAS, CAS cycling t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC -0.2 V Dout = High-Z CMOS interface RAS, CAS V CC -0.2 V Dout = High-Z t RC = min
Symbol I CC1 I CC2
Min -- --
--
1
--
1
--
1
mA
Standby current (L-version)
I CC2
--
200
--
200
--
200
A
RAS-only refresh current*2
I CC3
--
120
--
110
--
100
mA
6
HM514800C, HM51S4800C Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) *5 (cont)
HM514800C, HM51S4800C -6 Parameter Standby current
*1
-7 Max Min 5 --
-8 Max Min 5 -- Max Unit Test Conditions 5 mA RAS = VIH CAS = VIL Dout = enable t RC = min t PC = min Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 125 s t RAS 1 s, CAS = VIL WE = VIH CMOS interface RAS, CAS 0.2 V Dout = High-Z CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin 6.5 V 0 V Vout 6.5 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA
Symbol I CC5
Min --
CAS-before-RAS refresh current*4 Fast page mode current *1, 3 Battery backup current (Standby with CBR refresh) (L-version)
*4
I CC6 I CC7 I CC10
-- -- --
120 120 300
-- -- --
110 110 300
-- -- --
100 100 300
mA mA A
Self refresh mode current (HM51S4800C) Self refresh mode current (HM51S4800CL) Input leakage current Output leakage current Output high voltage Output low voltage
I CC11
--
1
--
1
--
1
mA
I CC11
--
200
--
200
--
200
A
I LI I LO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page cycle. 4. VIH V CC -0.2 V, VIL 0.2 V; Address can be changed once or less while CAS = VIL. 5. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
7
HM514800C, HM51S4800C Series
Capacitance (Ta = 25C, VCC = 5 V 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 10 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 10%, VSS = 0 V) *1, *14, *15
Test conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Input levels: 0 V, 3 V Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
HM514800C, HM51S4800C -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Symbol Min t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP 110 40 60 15 0 10 0 15 20 15 20 60 10 Max -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -7 Min 130 50 70 20 0 10 0 15 20 15 20 70 10 Max -- -- 10000 10000 -- -- -- -- 50 35 -- -- -- -8 Min 150 60 80 20 0 10 0 15 20 15 20 80 10 Max -- -- 10000 10000 -- -- -- -- 60 40 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 8 9 Notes
8
HM514800C, HM51S4800C Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) (cont)
HM514800C, HM51S4800C -6 Parameter OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol Min t ODD t DZO t DZC tT t REF t REF 15 0 0 3 -- -- Max -- -- -- 50 16 128 -7 Min 20 0 0 3 -- -- Max -- -- -- 50 16 128 -8 Min 20 0 0 3 -- -- Max -- -- -- 50 16 128 Unit ns ns ns ns ms ms 7 Notes
Read Cycle
HM514800C, HM51S4800C -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol Min t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t OFF1 t OFF2 t CDD -- -- -- -- 0 0 0 30 0 0 15 Max 60 15 30 15 -- -- -- -- 15 15 -- -7 Min -- -- -- -- 0 0 0 35 0 0 15 Max 70 20 35 20 -- -- -- -- 15 15 -- -8 Min -- -- -- -- 0 0 0 40 0 0 15 Max 80 20 40 20 -- -- -- -- 15 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns 6 6 Notes 2, 3 3, 4, 13 3, 5, 13
9
HM514800C, HM51S4800C Series
Write Cycle
HM514800C, HM51S4800C -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time CAS to OE delay time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH t COD 0 15 10 15 15 0 15 -- Max -- -- -- -- -- -- -- 0 -7 Min 0 15 10 20 20 0 15 -- Max -- -- -- -- -- -- -- 0 -8 Min 0 15 10 20 20 0 15 -- Max -- -- -- -- -- -- -- 0 Unit ns ns ns ns ns ns ns ns 11 11 18 Notes 10
Read-Modify-Write Cycle
HM514800C, HM51S4800C -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 150 80 35 50 15 Max -- -- -- -- -- -7 Min 180 95 45 60 20 Max -- -- -- -- -- -8 Min 200 105 45 65 20 Max -- -- -- -- -- Unit ns ns ns ns ns 10 10 10, 13 Notes
Refresh Cycle
HM514800C, HM51S4800C -6 Parameter CAS setup time (CAS-before-RAS refresh cycle) CAS hold time (CAS-before-RAS refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol Min t CSR t CHR t RPC t CPN 10 10 10 10 Max -- -- -- -- -7 Min 10 10 10 10 Max -- -- -- -- -8 Min 10 10 10 10 Max -- -- -- -- Unit ns ns ns ns Notes
10
HM514800C, HM51S4800C Series
Fast Page Mode Cycle
HM514800C, HM51S4800C -6 Parameter Fast page mode cycle time Symbol Min t PC 40 10 -- -- 35 55 Max -- -- -7 Min 45 10 Max -- -- -8 Min 50 10 Max -- -- Unit ns ns 12 3, 13 Notes
Fast page mode CAS precharge time t CP Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Fast page mode read-modify-write cycle CAS precharge to WE delay time Fast page mode read-modify-write cycle time t RASC t ACP t RHCP t CPW
100000 -- 35 -- -- -- 40 65
100000 -- 40 -- -- -- 45 70
100000 ns 45 -- -- ns ns ns
t PCM
80
--
95
--
100
--
ns
Self-refresh Mode
HM514800C, HM51S4800C -6 Parameter RAS pulse width (self-refresh) RAS precharge time (self-refresh) CAS hold time (self-refresh) Symbol Min t RASS t RPS t CHS 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit s ns ns Notes 19, 20, 21, 22
11
HM514800C, HM51S4800C Series
Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD t CWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among tAA, t CAC and t ACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 18. Do not enable Dout buffer when using delayed write timing. 19. Please do not use t RASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use t RPS instead of tRP. 20. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBRrefresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 21. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 s interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 22. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 23. XXX: H or L (H: VIH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout
12
HM514800C, HM51S4800C Series
When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
13
HM514800C, HM51S4800C Series
Timing Waveforms*23
Read Cycle
t RC t RAS
RAS tT t RCD t CSH t RSH t CAS t RP t CRP
CAS t ASR t RAD t RAH t ASC t RAL t CAH
Address
Row
Column
t RCS
t RCH
WE t CAC t AA High-Z Dout t RAC t DZC Din High-Z t OAC
t RRH t OFF1
Dout t OFF2 t CDD
t ODD t DZO
OE
14
HM514800C, HM51S4800C Series
Early Write Cycle
t RC t RAS
RAS tT t RCD t CSH CAS t RSH t CAS t CRP
t RP
t ASR t RAH t ASC t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z
* OE : V IH or V IL
15
HM514800C, HM51S4800C Series
Delayed Write Cycle
t RC t RAS
t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS t ASR t RAH t ASC t CAH Column t CWL t RWL
Address
Row
tRCS
t WP
WE t DS

t DH Din High-Z Din t DZC t DZO t ODD t OEH Dout t COD
Invalid Dout*
t OFF2
OE
* * Do not enable Dout during delayed write cycle.
16
HM514800C, HM51S4800C Series
Read-Modify-Write Cycle
t RWC t RP
RAS tT t RCD t CAS t CRP
CAS t ASR t RAD t RAH Address t ASC
tCAH
Row t RCS
Column t CWD t AWD t CWL t RWL t WP
WE t RWD t RAC t DZC Din
High-Z
t AA t CAC t DS t DH
Din
Dout t OAC
Dout
t OFF2 t DZO OE t ODD
t OEH
17
HM514800C, HM51S4800C Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP CAS t RPC t CRP
t RAH t ASR Address Row
Dout
High-Z
18
HM514800C, HM51S4800C Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS * t RP t RAS * t RC t RP
RAS tT t RPC t CPN t RPC t CHR t CPN t CSR t CHR t CRP t CSR

CAS Address t OFF1 Dout High-Z
, ,
> * Do not extend tRAS _ tRAS (max). Untested self refresh mode may be activated and loss of data may be resulted (HM514800C).
19
HM514800C, HM51S4800C Series
Fast Page Mode Read Cycle
t RASC t RHCP t RP
RAS tT t CSH t RCD CAS t ASR t RAD t RAH Address Row tASC t CAH t ASC tCAH Column t RCS t RCS WE t DZC t CDD Din High-Z t ODD t CAC t RAC t AA t DZC t CDD High-Z tCAC t AA t ACP t OFF1 Dout t OAC t DZO t OFF2 Dout t OAC t DZO t ODD t OFF2 Dout t OAC High-Z t CAC t AA t ACP t OFF1 t DZO Dout t OFF2 t ODD t OFF1 t DZC t CDD t RCH t RCH t ASC t RAL t CAH Column t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
Column
t RCS
t RRH t RCH
OE
20
HM514800C, HM51S4800C Series
Fast Page Mode Early Write Cycle
t RASC t RP
RAS t CSH tT t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
CAS
t ASR
t RAH
t ASC
t CAH
t ASC
t CAH
t ASC
t CAH
Address
Row
Column t WCS t WCH
Column t WCS t WCH t WCS
Column
t WCH
WE t DS t DS t DH t DH t DS t DH
Din
Din
Din
Din
Dout
High-Z
21
HM514800C, HM51S4800C Series
Fast Page Mode Delayed Write Cycle
t RASC t RP
RAS t CSH tT t RCD CAS t ASR t RAH t ASC t CAH t ASC t CAH t CWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t ASC t CAH
Address
Row
Column
Column
Column
t CWL t RCS t WP t WP
t CWL t WP t RWL
WE t DH t DS t RCS t DS t DH t RCS t DS t DH
Din
Din
Din
Din t OEH
Dout t ODD
High-Z
OE
22
HM514800C, HM51S4800C Series
Fast Page Mode Read-Modify-Write Cycle
t RP
t RASC RAS t RCD t CP t CAS CAS t RAD t RAH t ASR t CAH t ASC t ACP t ASC t CAH t CAH t ASC t CAS
tT
t PCM t CP t CAS t CRP
Address
Row
Column t AWD t CWD t RWD t CWL t WP t RCS
Column t AWD t CWD t CPW t CWL t WP
Column t CPW t AWD t RCS t CWD tCWL t RWL t WP
t RCS
WE t CAC t DS t DH High-Z tAA t RAC tOAC Dout t DZO Dout t OFF2 t DZO t OEH t OAC Dout t OFF2 tOEH t OAC Dout t OFF2 t OEH t DZC t CAC t DS t DH t ACP t DZC High-Z t CAC t DS t DH
t DZC
Din
Din
High-Z t AA
Din
Din
t DZO
OE t ODD t ODD t ODD
23
HM514800C, HM51S4800C Series
Self Refresh Cycle*19, 20, 21, 22
t RP
t RASS
t RPS
RAS tT t RPC t CPN t CRP t CHS t CSR

Address t OFF1 Dout High-Z 24
,
CAS
HM514800C, HM51S4800C Series
Package Dimensions
HM51(S)4800CJ/CLJ Series (CP-28D)
18.17 18.54 Max 28 15 10.16 0.13 11.18 0.13
Unit: mm
1 0.74
14
3.50 0.26
0.21 2.40 + 0.24 -
1.30 Max
0.43 0.10
1.27 0.10
0.80
+0.25 -0.17
9.40 0.25
25
HM514800C, HM51S4800C Series
HM51(S)4800CTT/CLTT Series (TTP-28D)
18.41 18.81 Max 28 15 Unit: mm
1 0.40 0.10
1.27 0.21 1.15 Max
M
14
10.16
11.76 0.20 0 - 5 0.80
0.10
0.17 0.05
0.13 0.05
1.20 Max
0.50 0.10
26

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